Centre closure

As part of a broader organisational restructure, data networking research at Swinburne University of Technology has moved from the Centre for Advanced Internet Architecture (CAIA) to the Internet For Things (I4T) Research Lab.

Although CAIA no longer exists, this website reflects CAIA's activities and outputs between March 2002 and February 2017, and is being maintained as a service to the broader data networking research community.

Set E 1msec Packet Inter-Arrival Time


The following section shows the difference between automatically allowing the interface to detect the line speed and explicitly setting the line speed of an interface for 1msec packet inter-arrival time.

Although explicitly setting the line speed in the 10Mbit/sec tests improved time stamp accuracy, this was not the case for the 100Mbit/sec tests due to outliers.

Figure 38: Automatic 10Mbit/sec
Figure 39: Explicit 10Mbit/sec
Figure 40: Automatic 100Mbit/sec
Figure 41: Explicit 100Mbit/sec

We can see from Tables 37 to 40 that explicitly setting the line speed with a packet transmission inter-packet gap of 1msec did not improve time stamp accuracy for the 100Mbit/sec test. This was mainly due to two time stamp outliers.

Table 37: Automatic 10Mbit/sec (usec)

Mean
Variance
Standard Deviation
1083.294
1.097
1.047

Table 38: Explicit 10Mbit/sec (usec)

Mean
Variance
Standard Deviation
1083.294
1.022
1.011

Table 39: Automatic 100Mbit/sec (usec)

Mean
Variance
Standard Deviation
1008.408
0.943
0.971

Table 40: Explicit 100Mbit/sec (usec)

Mean
Variance
Standard Deviation
1008.407
1.029
1.015




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