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Evaluating ASUS P4P800VM ATX Motherboards
CAIA Technical Report 040513A

Ana M. Pavlicic
May 13th, 2004

Introduction

This technical report outlines the results obtained from testing a new CAIA PC containing an ASUS P4P800VM ATX Motherboard. The process used to test the timestamping accuracy of the PC was the same as that used to evaluate a new BART project PC. Tcpdump on the PC was used to capture packets and the time stamping of the packets were investigated in this report. The aim of the investigation was to find the optimal configuration for Ethernet interfaces so as to obtain the most accurate time stamp results.

Equipment and Setup

The tests conducted involved two link speeds, 10Mbit/sec and 100Mbit/sec, with 32,000 UDP packets at 92 bytes + 4 bytes CRC long flooded to the PC under evaluation. Packet inter-arrival time set on SmartBits2000 was 500usec and 1msec for each of the link speed tests. The inter-arrival time used by SmartBits2000 and the Tcpdump time stamps differ in the way they are measured. SmartBits2000 measures inter-arrival time as the time between the end of one packet and the start of the next packet. The Tcpdump -ttt option measures the time from the beginning of one packet to the start of the next packet. In this case, the size of the packet is included into the time interval. To learn more about SmartBits2000 inter-arrival time, tcpdump -ttt time stamps and time offsets see Mark Pozzobon's report. All time stamps should be the inter-arrival time of packets as sent by the SmartBits2000 plus approximately 83usec (83.2usec) for the 10Mbit/sec line speed and 8.3usec for the 100Mbit/sec line speed.

Each inter-arrival time was tested using a single SmartBits2000 card flooding packets to the PC's Ethernet port. Initially the interface configuration was allowed to automatically adjust to 10Mbit/sec or 100Mbit/sec traffic, then the line speed on the interface was explicity (statically) set at 10Mbit/sec or 100Mbit/sec. SmartBits2000 flooded packets at the line speed under testing. This was to investigate whether there is a difference when the interface is automatically detecting the line speed and when it is explicitly set to 10Mbit/sec or 100Mbit/sec. Figure 1 below illustrates the test setup.


Figure 1: Hardware Setup


Tcpdump was run with the following command: "tcpdump -n -i interface -w filename" then packet time stamps placed into a separate file using the command: "tcdpump -n -ttt -r filename | awk -F " " '{print $1}' > newfilename" for analysis.

Test Set A to E: The results were obtained using the following equipment:
  • Netcom System SmartBits2000 Multiport Performance Analysis System with one SX-7410 100Mb Ethernet TP card
  • Tcpdump running on the test PC with the following configuration:
    • Intel Celeron 2.4GHz (400) Single Processor
    • ASUS P4P800VM ATX Motherboard
    • Intel 865G Chipset 10/100 Mbps LAN on-board NIC (Ethernet interface fpx0)
    • 256MB PC3200 DDRAM High Speed Memory
  • Two CAT5 UTP Crossover cables
  • Separate PC running Netcom Systems SmartWindow v6.51 to control the packets being flooded by SmartBits2000
Test Set A, B, C and D: These tests included the presence of the following NIC:
  • Intel Pro100 PCO 10/100 NIC (Ethernet interface fxp1)

Results/Discussion

The following are the results obtained in the investigation by test sets A, B, C, D and E. All mean, variance and standard deviaton time stamp results have been rounded to three decimal places:

Test Set A: Interface fxp0 tested

The first step of the investigation was to test the in-built Ethernet card by allowing the interface to automatically detect the line speed as set on the SmartBits2000. This was followed by explicitly setting the correct line speed (either 10Mbit/sec or 100Mbit/sec) for each of the inter-arrival times tested. The second interface, fxp1, was down during these tests.

The results obtained showed that a slight improvement occurs when the line speed is explicitly configured, rather than just allowing the line speed to be automatically detected by the fxp0 interface.

500usec Packet Inter-Arrival Time
1msec Packet Inter-Arrival Time

Test Set B: Interface fxp1 tested with fxp0 up but no carrier present

In this set of results, the fxp1 interface was receiving the packets sent from the SmartBits2000. The fxp0 interface was up but there was no carrier line, thus it was not active.

Result obtained indicated an increase in outliers affecting the time stamp accuracy. Explicitly setting the line speed slightly improved time stamp accuracy due to reduction of outliers over automatic line speed detection in all cases but for the 1msec, 10Mbit/sec tests.

500usec Packet Inter-Arrival Time
1msec Packet Inter-Arrival Time

Test Set C: Interface fxp1 tested with fxp0 up with carrier present

In this set of results, the fxp1 interface was receiving the packets sent from the SmartBits2000. The fxp0 interface, was up and a carrier was present. The fxp0 interface was explicitly set to 100Mbit/sec.

Result obtained indicated an increase in outliers affecting the time stamp accuracy. Explicitly setting the line speed only slightly improved time stamp accuracy over automatic line speed detection in all cases but for the 1msec, 10Mbit/sec tests. This is the same behaviour as seen in Set B.

500usec Packet Inter-Arrival Time
1msec Packet Inter-Arrival Time

Test Set D: Interface fxp1 tested with fxp0 down and no carrier present

In this set of results, the fxp1 interface was receiving the packets sent from the SmartBits2000. The fxp0 interface, was down and a carrier was not present. The fxp0 interface was explicitly set to 100Mbit/sec for consistency.

Result obtained indicated only a slight improvement of time stamp accuracy with the reduction in the number of time stamp outliers for explicitly set line speeds.

500usec Packet Inter-Arrival Time
1msec Packet Inter-Arrival Time

Test Set E: Interface fxp0 tested with the fxp1 interface removed from the PC

In this set of results, the fxp0 interface was receiving the packets sent from the SmartBits2000.

Result obtained indicated a minimal time stamp accuracy improvement for explicitly set line speeds, except for the 1msec, 100Mbit/sec test due to outliers.

500usec Packet Inter-Arrival Time
1msec Packet Inter-Arrival Time

Summary and Further Investigation

As seen in this investigation, all the tests resulted in basically the same time stamp distribution, with a minor increase in the number of random outliers throughout the test data when auto-detection of line speed was used. Generally, explicitly setting the line speed on an interface improved time stamp accuracy, although only very slightly. We can see that unlike previous PC testing there was no significant improvement in time stamp accuracy by using this approach.

Table 41 summarises the configurations which produced the smallest variance and standard deviation in time stamps. Ignoring the fact that a minuscule number of outliers affected the variance and standard deviation results, the best results were obtained when there was either no fxp1 interface or when it was down. Table 42 summarises the configurations which produced the largest variance and standard deviation in time stamps. Once again ignoring the fact that a minuscule number of outliers affected the variance and standard deviation results, the worst results were obtained when the fxp1 interface was present and tested.

Test Configuration
Optimum Result Configuration
Variance
Standard Deviation
500usec 10Mbit/sec
Explicitly set line speed Test E
0.928
0.963
500usec 100Mbit/sec
Explicitly set line speed Test A
0.927
0.963
1msec 10Mbit/sec
Explicitly set line speed Test E
1.022
1.011
1msec 100Mbit/sec
Explicitly set line speed Test A
0.882
0.939

Table 41: Optimum Performance Results


Test Configuration
Worst Result Configuration
Variance
Standard Deviation
500usec 10Mbit/sec
Automatic line speed detection Test C
1.738
1.318
500usec 100Mbit/sec
Automatic line speed detection Test D
1.665
1.290
1msec 10Mbit/sec
Explicitly set line speed Test B
1.321
1.149
1msec 100Mbit/sec
Automatic line speed detection Test B
1.811
1.346

Table 42: Worst Performance Results


Further investigation will include testing time stamp accuracy of other PCs at CAIA.

Acknowledgements

Grenville Armitage, Director of Centre for Advanced Internet Architectures.





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Maintained by: Ana Pavlicic apavlicic@groupwise.swin.edu.au
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