Centre closure

As part of a broader organisational restructure, data networking research at Swinburne University of Technology has moved from the Centre for Advanced Internet Architecture (CAIA) to the Internet For Things (I4T) Research Lab.

Although CAIA no longer exists, this website reflects CAIA's activities and outputs between March 2002 and February 2017, and is being maintained as a service to the broader data networking research community.

This page is part of the BART project.

Set B 50msec Packet Inter-Arrival Time


The following section discusses the difference between automatically allowing the interface to detect the line speed and explicitly setting the line speed of an interface for 50msec packet inter-arrival time for Set B.

In Figures 38 to 41, the mean time stamp is far enough from zero to show the symmetric pattern produced by the time stamp outliers.

Figure 38: Automatic 10Mbit/sec
Figure 39: Explicit 10Mbit/sec
Figure 40: Automatic 100Mbit/sec
Figure 41: Explicit 100Mbit/sec

Tables 33 to 36 show that the mean values are still close to the theoretical values of 50083usec for 10Mbit/sec and 50008.3usec for 100Mbit/sec while the variance and standard deviation are very large.

Table 33: Automatic 10Mbit/sec (usec)

Mean
Varience
Standard Deviation
50083.72
200894.80
448.21

Table 34: Explicit 10Mbit/sec (usec)

Mean
Varience
Standard Deviation
50083.74
198314.20
445.32

Table 35: Automatic 100Mbit/sec (usec)

Mean
Varience
Standard Deviation
50008.82
209105.20
457.28

Table 36: Explicit 100Mbit/sec (usec)

Mean
Varience
Standard Deviation
50008.83
186779.70
432.18




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