Centre closure

As part of a broader organisational restructure, data networking research at Swinburne University of Technology has moved from the Centre for Advanced Internet Architecture (CAIA) to the Internet For Things (I4T) Research Lab.

Although CAIA no longer exists, this website reflects CAIA's activities and outputs between March 2002 and February 2017, and is being maintained as a service to the broader data networking research community.

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Set A 50msec Packet Inter-Arrival Time


The following section discusses the difference between automatically allowing the interface to detect the line speed and explicitly setting the line speed of an interface for 50msec packet inter-arrival time for Set A.

An error in one time stamp causes consecutive inter-packet intervals to be skewed equally in opposite directions about the mean. This leads to the symmetric patterns in Figures 14 and 16 when the receiving interface is configured to automatically detect line speed. These patterns were not was obvious in the 125usec, 500usec and 1msec inter-arrival time results.

Figure 14: Automatic 10Mbit/sec
Figure 15: Explicit 10Mbit/sec
Figure 16: Automatic 100Mbit/sec
Figure 17: Explicit 100Mbit/sec

Tables 13, 14, 15 and 16 once again show that explicitly setting the line speed on the interface causes the variance and standard deviation to be smaller.

Table 13: Automatic 10Mbit/sec (usec)

Mean
Varience
Standard Deviation
50083.73
74232.98
272.46

Table 14: Explicit 10Mbit/sec (usec)

Mean
Varience
Standard Deviation
50083.72
1.92
1.38

Table 15: Automatic 100Mbit/sec (usec)

Mean
Varience
Standard Deviation
50008.86
80132.26
283.08

Table 16: Explicit 100Mbit/sec (usec)

Mean
Varience
Standard Deviation
50008.87
1.75
1.32




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