As part of a broader organisational restructure, data networking research at Swinburne University of Technology has moved from the Centre for Advanced Internet Architecture (CAIA) to the Internet For Things (I4T) Research Lab.

Although CAIA no longer exists, this website reflects CAIA's activities and outputs between March 2002 and February 2017, and is being maintained as a service to the broader data networking research community.


This page is part of the BART project.

Set B 500usec Packet Inter-Arrival Time


The following section discusses the difference between automatically allowing the interface to detect the line speed and explicitly setting the line speed of an interface for 500usec packet inter-arrival time for Set B.

Figures 30 to 33 show an interesting three-tier pattern produced by the time stamps. Again, statically setting the line speed to explicitly be 10Mbit/sec or 100Mbit/sec results in no improvement in time stamp performance.

Figure 30: Automatic 10Mbit/sec
Figure 31: Explicit 10Mbit/sec
Figure 32: Automatic 100Mbit/sec
Figure 33: Explicit 100Mbit/sec

Tables 25 to 28 support the claim that there is no improvement in time stamp accuracy when the line speed of the inerface receiving the packets is explicitly set to 10Mbit/sec or 100Mbit/sec.

Table 25: Automatic 10Mbit/sec (usec)

Mean
Varience
Standard Deviation
583.21
30424.87
174.43

Table 26: Explicit 10Mbit/sec (usec)

Mean
Varience
Standard Deviation
583.21
30102.54
173.50

Table 27: Automatic 100Mbit/sec (usec)

Mean
Varience
Standard Deviation
508.32
25761.38
160.50

Table 28: Explicit 100Mbit/sec (usec)

Mean
Varience
Standard Deviation
508.31
24457.71
156.39






Swinburne Homepage Site Map Search Index
 

Swinburne Copyright and disclaimer Privacy Feedback

Last Updated: Tuesday 2-Dec-2003 09:46:42 AEDT
URL:
Maintained by: Ana Pavlicic apavlicic@groupwise.swin.edu.au
Authorised by: Grenville Armitage garmitage@swin.edu.au

IndexSearchSite MapSwinburne Home Page