As part of a broader organisational restructure, data networking research at Swinburne University of Technology has moved from the Centre for Advanced Internet Architecture (CAIA) to the Internet For Things (I4T) Research Lab.

Although CAIA no longer exists, this website reflects CAIA's activities and outputs between March 2002 and February 2017, and is being maintained as a service to the broader data networking research community.


This page is part of the BART project.

Set B 1msec Packet Inter-Arrival Time


The following section discusses the difference between automatically allowing the interface to detect the line speed and explicitly setting the line speed of an interface for 1msec packet inter-arrival time for Set B.

As seen in Figures 34 to 37, the three-tier effect also occurs when the packet inter-arrival time is set to 1msec. Since negative time is impossible, the patterns do not appear symmetrical about the mean.

Figure 34: Automatic 10Mbit/sec
Figure 35: Explicit 10Mbit/sec
Figure 36: Automatic 100Mbit/sec
Figure 37: Explicit 100Mbit/sec

Tables 29 to 32 again show that for all configurations of the line speed (both auto-detect and static) the varience and standard deviation are very large.

Table 29: Automatic 10Mbit/sec (usec)

Mean
Varience
Standard Deviation
1083.21
54052.28
232.49

Table 30: explicit 10Mbit/sec (usec)

Mean
Varience
Standard Deviation
1083.21
54195.47
232.80

Table 31: Automatic 100Mbit/sec (usec)

Mean
Varience
Standard Deviation
1008.33
50107.46
223.85

Table 32: Explicit 100Mbit/sec (usec)

Mean
Varience
Standard Deviation
1008.33
49048.92
221.47





Swinburne Homepage Site Map Search Index
 

Swinburne Copyright and disclaimer Privacy Feedback

Last Updated: Tuesday 2-Dec-2003 09:46:21 AEDT
URL:
Maintained by: Ana Pavlicic apavlicic@groupwise.swin.edu.au
Authorised by: Grenville Armitage garmitage@swin.edu.au

IndexSearchSite MapSwinburne Home Page