Centre closure

As part of a broader organisational restructure, data networking research at Swinburne University of Technology has moved from the Centre for Advanced Internet Architecture (CAIA) to the Internet For Things (I4T) Research Lab.

Although CAIA no longer exists, this website reflects CAIA's activities and outputs between March 2002 and February 2017, and is being maintained as a service to the broader data networking research community.

This page is part of the BART project.

Set B 100msec Packet Inter-Arrival Time


The following section discusses the difference between automatically allowing the interface to detect the line speed and explicitly setting the line speed of an interface for 100msec packet inter-arrival time for Set B.

As with all other time stamp results for the Intel NIC tested, there is no improvement in time stamp performance for explicitly setting the line speed compared to configuring the interface to automatically detect the line speed. This can be seen in Figures 42 to 45.

Figure 42: Automatic 10Mbit/sec
Figure 43: Explicit 10Mbit/sec
Figure 44: Automatic 100Mbit/sec
Figure 45: Explicit 100Mbit/sec

Tables 37 to 40 support all previous findings for the Intel NIC used.

Table 37: Automatic 10Mbit/sec (usec)

Mean
Varience
Standard Deviation
100084.30
197855.90
444.81

Table 38: Explicit 10Mbit/sec (usec)

Mean
Varience
Standard Deviation
100084.30
196099.70
442.83

Table 39: Automatic 100Mbit/sec (usec)

Mean
Varience
Standard Deviation
100009.30
232007.10
481.67

Table 40: Explicit 100Mbit/sec (usec)

Mean
Varience
Standard Deviation
100009.40
172435.70
414.25




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