As part of a broader organisational restructure, data networking research at Swinburne University of Technology has moved from the Centre for Advanced Internet Architecture (CAIA) to the Internet For Things (I4T) Research Lab.

Although CAIA no longer exists, this website reflects CAIA's activities and outputs between March 2002 and February 2017, and is being maintained as a service to the broader data networking research community.

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Calibration Tests for Intel CA810e based computer

This test was used to determine the accuracy of the Intel CA810e with bursts of fixed-spaced ethernet packets. In particular, to look at the effects of an additional network card to the configuration with respect to the timestamping of packets.

Figure 7.
Setup of Hardware for Intel CA810e Packet Sniffing Computer Calibration

Tests cases conducted were:
Interval Duration
125usec (124.8usec) 5min
300usec 2min
1000usec 2min
5000usec 2min


The tables below detail the Mean, Variance and Standard Deviation values for the test cases generated. All values are in microseconds.

Interval Without Interface vr0 With Interface vr0
Mean Var Std Dev Mean Var Std Dev
125usec 208.0 7.0 2.6 208.0 1362.9 36.9
300usec 383.2 7.6 2.8 383.2 2431.4 49.3
1000usec 1083.1 4.7 2.2 1083.1 6643.6 81.5
5000usec 5083.0 4.0 2.0 5083.0 11042.0 105.1

125usec Interval, without vr0
Figure 8.
125usec Interval, with vr0
Figure 9.
300usec Interval, without vr0
Figure 10.
300usec Interval, with vr0
Figure 11.
1000usec Interval, without vr0
Figure 12.
1000usec Interval, with vr0
Figure 13.
5000usec Interval, without vr0
Figure 14.
5000usec Interval, with vr0
Figure 15.

Note: Although the above tests were run for 5 minutes duration, only a snap shot of this data is shown above due to limitations with Microsoft Excel. The entire data that was collected has been checked and is consistent with the above representative samples.

From the results above it can observed that an interesting time stamping error with interface vr0 present (2nd network card installed). This error occurs every second, whereby a packet is incorrectly time stamped up to 2.5 milliseconds greater than the mean interpacket arrival time. This behaviour was only seen on the CA810e-based system (600MHz Celeron CA810e Intel motherboard running FreeBSD 4.6).

Also note, that for the graphs above with vr0 present the duration between each of the outlying time stamped packets was approximately 1 second. Hence, the number of packets between these outliers is dependent upon the fixed-space interval for each test case (ie. The smaller fixed-interval the greater the number of packets between outliers and vice-versa).


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Last Updated: Tuesday 24-Sep-2002 12:34:14 AEST
Maintained by: Grenville Armitage
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